 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ltc2220/ltc2221 1 22201fa features descriptio u typical applicatio u 12-bit,170msps/ 135msps adcs the ltc ? 2220 and ltc2221 are 170msps/135msps, sam- pling 12-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. the ltc2220/ ltc2221 are perfect for demanding communications applications with ac performance that includes 67.5db snr and 80db spurious free dynamic range for signals up to 170mhz. ultralow jitter of 0.15ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 0.4lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.5lsb rms . the digital outputs can be either differential lvds, or single-ended cmos. there are three format options for the cmos outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc C inputs may be driven differentially or single ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. C + input s/h correction logic output drivers 12-bit pipelined adc core clock/duty cycle control flexible reference d11 ? ? ? d0 encode input refh refl analog input 22201 ta01 cmos or lvds 0.5v to 3.6v 3.3v v dd ov dd ognd applicatio s u sfdr vs input frequency 0 600 500 400 100 200 300 input frequency (mhz) sfdr (dbfs) 80 90 100 22201 ta01b 70 60 40 50 4th or higher 2nd or 3rd , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. sample rate: 170msps/135msps 67.5db snr up to 140mhz input 80db sfdr up to 170mhz input 775mhz full power bandwidth s/h single 3.3v supply low power dissipation: 890mw/660mw lvds, cmos, or demultiplexed cmos outputs selectable input ranges: 0.5v or 1v no missing codes optional clock duty cycle stabilizer shutdown and nap modes data ready output clock pin compatible family 185msps: ltc2220-1 (12-bit) 170msps: ltc2220 (12-bit), ltc2230 (10-bit) 135msps: ltc2221 (12-bit), ltc2231 (10-bit) 64-pin 9mm 9mm qfn package wireless and wired broadband communication cable head-end systems power amplifier linearization communications test equipment
ltc2220/ltc2221 2 22201fa co verter characteristics u supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... C0.3v to 1v analog input voltage (note 3) ..... C0.3v to (v dd + 0.3v) digital input voltage .................... C0.3v to (v dd + 0.3v) digital output voltage ............... C0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range ltc2220c, ltc2221c ............................. 0 c to 70 c ltc2220i, ltc2221i ...........................C40 c to 85 c storage temperature range ..................C65 c to 125 c absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) ltc2220 ltc2221 parameter conditions min typ max min typ max units resolution (no missing codes) 12 12 bits integral linearity error differential analog input (note 5) C1.5 0.4 1.5 C1 0.4 1 lsb differential linearity error differential analog input C1 0.3 1 C1 0.2 1 lsb integral linearity error single-ended analog input (note 5) 1 1lsb differential linearity error single-ended analog input 0.3 0.2 lsb offset error (note 6) C35 3 35 C35 335 mv gain error external reference C2.5 0.5 2.5 C2.5 0.5 2.5 %fs offset drift 10 10 v/c full-scale drift internal reference 30 30 ppm/c external reference 15 15 ppm/c transition noise sense = 1v 0.5 0.5 lsb rms t jmax = 125 c, ja = 20 c/w exposed pad (pin 65) is gnd, must be soldered to pcb order part number consult ltc marketing for parts specified with wider operating temperature ranges. the temperature grade is identified by a label on the shipping container. ltc2220cup ltc2220iup ltc2221cup ltc2221iup order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ up part marking* ltc2220up ltc2220up ltc2221up ltc2221up top view up package 64-lead (9mm 9mm) plastic qfn a in + 1 a in + 2 a in C 3 a in C 4 refha 5 refha 6 reflb 7 reflb 8 refhb 9 refhb 10 refla 11 refla 12 v dd 13 v dd 14 v dd 15 gnd 16 48 d9 + /da6 47 d9 C /da5 46 d8 + /da4 45 d8 C /da3 44 d7 + /da2 43 d7 C /da1 42 ov dd 41 ognd 40 d6 + /da0 39 d6 C /clockouta 38 d5 + /clockoutb 37 d5 C /ofb 36 clockout + /db11 35 clockout C /db10 34 ov dd 33 ognd 64 gnd 63 v dd 62 v dd 61 gnd 60 v cm 59 sense 58 mode 57 lvds 56 of + /ofa 55 of C /da11 54 d11 + /da10 53 d11 C /da9 52 d10 + /da8 51 d10 C /da7 50 ognd 49 ov dd enc + 17 enc C 18 shdn 19 oe 20 do C /db0 21 do + /db1 22 d1 C /db2 23 d1 + /db3 24 ognd 25 ov dd 26 d2 C /db4 27 d2 + /db5 28 d3 C /db6 29 d3 + /db7 30 d4 C /db8 31 d4 + /db9 32 65 ltc2220/ltc2221 3 22201fa symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.1v < v dd < 3.5v (note 7) 0.5 to 1v v in, cm analog input common mode (a in + + a in C )/2 differential input (note 7) 1 1.6 1.9 v single ended input (note 7) 0.5 1.6 2.1 v i in analog input leakage current 0 < a in + , a in C < v dd C1 1 a i sense sense input leakage 0v < sense < 1v C1 1 a i mode mode pin pull-down current to gnd 10 a i lvds lvds pin pull-down current to gnd 10 a t ap sample and hold acquisition delay time 0 ns t jitter sample and hold acquisition delay time jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 775 mhz ltc2220 ltc2221 symbol parameter conditions min typ max min typ max units snr signal-to-noise ratio 5mhz input (1v range) 62.7 62.8 db (note 10) 5mhz input (2v range) 67.7 67.8 db 70mhz input (1v range) 62.7 62.8 db 70mhz input (2v range) 65.8 67.6 65.8 67.8 db 140mhz input (1v range) 62.4 62.5 db 140mhz input (2v range) 67.5 67.5 db 250mhz input (1v range) 61.8 61.8 db 250mhz input (2v range) 66.1 66.1 db sfdr spurious free dynamic range 5mhz input (1v range) 84 84 db 2nd or 3rd harmonic 5mhz input (2v range) 84 84 db 70mhz input (1v range) 84 84 db 70mhz input (2v range) 70 84 70 84 db 140mhz input (1v range) 84 84 db 140mhz input (2v range) 84 84 db 250mhz input (1v range) 74 77 db 250mhz input (2v range) 73 77 db sfdr spurious free dynamic range 5mhz input (1v range) 90 90 db 4th harmonic or higher 5mhz input (2v range) 90 90 db 70mhz input (1v range) 90 90 db 70mhz input (2v range) 75 90 75 90 db 140mhz input (1v range) 87 90 db 140mhz input (2v range) 87 90 db 250mhz input (1v range) 85 90 db 250mhz input (2v range) 85 90 db s/(n+d) signal-to-noise plus 5mhz input (1v range) 62.7 62.8 db distortion ratio (note 12) 5mhz input (2v range) 67.5 67.6 db 70mhz input (1v range) 62.7 62.8 db 70mhz input (2v range) 65 67.3 65 67.4 db imd intermodulation distortion f in1 = 138mhz, f in2 = 140mhz 81 81 dbc a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) (note 11) (note 11) ltc2220/ltc2221 4 22201fa digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.570 1.600 1.630 v v cm output tempco 25 ppm/ c v cm line regulation 3.1v < v dd < 3.5v 3 mv/v v cm output resistance C1ma < i out < 1ma 4 ? symbol parameter conditions min typ max units encode inputs (enc + , enc ) v id differential input voltage 0.2 v v icm common mode input voltage internally set 1.6 v externally set (note 7) 1.1 1.6 2.5 v r in input resistance 6k ? c in input capacitance (note 7) 3 pf logic inputs (oe, shdn) v ih high level input voltage v dd = 3.3v 2v v il low level input voltage v dd = 3.3v 0.8 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf logic outputs (cmos mode) ov dd = 3.3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3.3v 50 ma v oh high level output voltage i o = C10 a 3.295 v i o = C200 a 3.1 3.29 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = C200 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v logic outputs (lvds mode) v od differential output voltage 100 ? differential load 247 350 454 mv v os output common mode voltage 100 ? differential load 1.125 1.250 1.375 v ltc2220/ltc2221 5 22201fa ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 9) ltc2220 ltc2221 symbol parameter conditions min typ max min typ max units v dd analog supply voltage (note 8) 3.1 3.3 3.5 3.1 3.3 3.5 v p shdn shutdown power shdn = high, oe = high, no clk 2 2 mw p nap nap mode power shdn = high, oe = low, no clk 35 35 mw lvds output mode ov dd output supply voltage (note 8) 3 3.3 3.6 3 3.3 3.6 v i vdd analog supply current 264 288 196 212 ma i ovdd output supply current 55 70 55 70 ma p diss power dissipation 1050 1182 828 931 mw cmos output mode ov dd output supply voltage (note 8) 0.5 3.3 3.6 0.5 3.3 3.6 v i vdd analog supply current 264 288 196 212 ma p diss power dissipation 890 660 mw ltc2220 ltc2221 symbol parameter conditions min typ max min typ max units f s sampling frequency (note 8) 1 170 1 135 mhz t l enc low time (note 7) duty cycle stabilizer off 2.8 2.94 500 3.5 3.7 500 ns duty cycle stabilizer on 2 2.94 500 2 3.7 500 ns t h enc high time (note 7) duty cycle stabilizer off 2.8 2.94 500 3.5 3.7 500 ns duty cycle stabilizer on 2 2.94 500 2 3.7 500 ns t ap sample-and-hold aperture delay 0 0 ns t oe output enable delay (note 7) 510 510 ns lvds output mode t d enc to data delay (note 7) 1.3 2.2 3.5 1.3 2.2 3.5 ns t c enc to clockout delay (note 7) 1.3 2.2 3.5 1.3 2.2 3.5 ns data to clockout skew (t c - t d ) (note 7) C0.6 0 0.6 C0.6 0 0.6 ns rise time 0.5 0.5 ns fall time 0.5 0.5 ns pipeline latency 5 5 cycles cmos output mode t d enc to data delay (note 7) 1.3 2.1 3.5 1.3 2.1 3.5 ns t c enc to clockout delay (note 7) 1.3 2.1 3.5 1.3 2.1 3.5 ns data to clockout skew (t c - t d ) (note 7) C0.6 0 0.6 C0.6 0 0.6 ns pipeline latency full rate cmos 5 5 cycles demuxed interleaved 5 5 cycles demuxed simultaneous 5 and 6 5 and 6 cycles ltc2220/ltc2221 6 22201fa input frequency (mhz) 0 snr (dbfs) 70 69 68 67 66 65 64 63 62 61 60 600 500 400 2220 g04 snr (dbfs) 70 69 68 67 66 65 64 63 62 61 60 100 200 300 input frequency (mhz) 0 600 500 400 100 200 300 0 600 500 400 100 200 300 2220 g05 input frequency (mhz) sfdr (dbfs) 80 90 100 2220 g06 70 60 40 50 output code 0 error (lsb) 4096 2220 g01 1024 2048 3072 0 4096 1024 2048 3072 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 output code error (lsb) 2220 g02 code 2056 229 140 12866 24266 93571 count 100000 80000 60000 40000 20000 C0 2060 2220 g03 2057 2058 2059 typical perfor a ce characteristics uw note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 170mhz (ltc2220) or 135mhz (ltc2221), lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a best straight line fit to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. note 9: v dd = 3.3v, f sample = 170mhz (ltc2220) or 135mhz (ltc2221), differential enc + /enc C = 2v p-p sine wave, input range = 1v p-p with differential drive, output c load = 5pf. note 10: snr minimum and typical values are for lvds mode. typical values for cmos mode are typically 0.3db lower. note 11: sfdr minimum values are for lvds mode. typical values are for both lvds and cmos modes. note 12: sinad minimum and typical values are for lvds mode. typical values for cmos mode are typically 0.3db lower. electrical characteristics ltc2220: inl, 2v range ltc2220: dnl, 2v range ltc2220: shorted input noise histogram (t a = 25 c unless otherwise noted, note 4) ltc2220: snr vs input frequency, ?db, 2v range, lvds mode ltc2220: sfdr (hd2 and hd3) vs input frequency, ?db, 2v range, lvds mode ltc2220: snr vs input frequency, ?db, 1v range, lvds mode ltc2220/ltc2221 7 22201fa 0 600 500 400 100 200 300 input frequency (mhz) sfdr (dbfs) 80 90 100 2220 g07 70 60 40 50 0 600 500 400 100 200 300 input frequency (mhz) sfdr (dbfs) 80 90 100 2220 g08 70 60 40 50 0 600 500 400 100 200 300 input frequency (mhz) sfdr (dbfs) 80 90 100 2220 g09 70 60 40 50 sfdr and snr (dbfs) 95 90 85 80 75 70 65 60 55 50 sample rate (msps) 2220 g10 040 80 120 160 200 sfdr and snr (dbfs) 95 90 85 80 75 70 65 60 55 50 290 280 270 260 250 240 230 220 210 sample rate (msps) 2220 g11 040 80 120 160 200 sample rate (msps) 2220 g12 040 80 120 160 200 sample rate (msps) 2220 g13 040 80 120 160 200 2v range 1v range input level (dbfs) C60 sfdr (dbc and dbfs) C50 C40 C30 C20 2220 g14 C10 100 90 80 70 60 50 40 30 20 10 0 0 i ovdd (ma) i vdd (ma) 60 50 40 30 20 10 0 dbfs dbc lvds outputs, 0v dd = 3.3v cmos outputs, 0v dd = 1.8v sfdr snr sfdr snr ltc2220: sfdr (hd2 and hd3) vs input frequency, ?db, 1v range, lvds mode ltc2220: sfdr (hd4+) vs input frequency, ?db, 2v range, lvds mode ltc2220: sfdr (hd4+) vs input frequency, ?db, 1v range, lvds mode typical perfor a ce characteristics uw ltc2220: sfdr and snr vs sample rate, 1v range, f in = 30mhz, ?db, lvds mode ltc2220: sfdr and snr vs sample rate, 2v range, f in = 30mhz, ?db, lvds mode ltc2220: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2220: i ovdd vs sample rate, 5mhz sine wave input, ?db ltc2220: sfdr vs input level, f in = 70mhz, 2v range ltc2220/ltc2221 8 22201fa amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g15 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g16 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g17 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g19 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g20 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g18 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g21 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g22 frequency (mhz) 0 40 60 10 20 50 70 80 30 amplitude (db) 0 C20 C40 C60 C80 C100 C120 2220 ? g23 frequency (mhz) 0 40 60 10 20 50 70 80 30 typical perfor a ce characteristics uw ltc2220: 8192 point fft, f in = 30mhz, ?db, 2v range, lvds mode ltc2220: 8192 point fft, f in = 30mhz, ?db, 1v range, lvds mode ltc2220: 8192 point fft, f in = 70mhz, ?db, 2v range, lvds mode ltc2220: 8192 point fft, f in = 70mhz, ?db, 1v range, lvds mode ltc2220: 8192 point fft, f in = 140mhz, ?db, 2v range, lvds mode ltc2220: 8192 point fft, f in = 140mhz, ?db, 1v range, lvds mode ltc2220: 8192 point fft, f in = 250mhz, ?db, 2v range, lvds mode ltc2220: 8192 point fft, f in = 250mhz, ?db, 1v range, lvds mode ltc2220: 8192 point fft, f in = 500mhz, ?db, 1v range, lvds mode ltc2220/ltc2221 9 22201fa 79331 21767 123 322 29529 100000 80000 60000 40000 20000 0 2058 2059 2060 2061 2057 input frequency (mhz) 0 snr (dbfs) 69 67 65 63 61 59 57 55 600 500 400 2221 g04 100 200 300 input frequency (mhz) 0 snr (dbfs) sfdr (dbfs) 69 67 65 63 61 59 57 55 600 500 400 2221 g05 100 200 300 input frequency (mhz) 0 600 500 400 2221 g06 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2221 g07 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2221 g09 100 200 300 95 90 85 80 75 70 65 60 55 50 sfdr (dbfs) input frequency (mhz) 0 600 500 400 2221 g08 100 200 300 95 90 85 80 75 70 65 60 55 50 2221 g02 2221 g03 count output code 0 4096 2221 g01 1024 2048 3072 output code code 0 4096 1024 2048 3072 1.0 0.8 0.6 0.4 0.2 0 C 0.2 C 0.4 C 0.6 C 0.8 C 1.0 error (lsb) 1.0 0.8 0.6 0.4 0.2 0 C 0.2 C 0.4 C 0.6 C 0.8 C 1.0 error (lsb) typical perfor a ce characteristics uw ltc2221: inl, 2v range ltc2221: dnl, 2v range ltc2221: shorted input noise histogram ltc2221: snr vs input frequency, ?db, 2v range, lvds mode ltc2221: sfdr (hd2 and hd3) vs input frequency, ?db, 2v range, lvds mode ltc2221: snr vs input frequency, ?db, 1v range, lvds mode ltc2221: sfdr (hd2 and hd3) vs input frequency, ?db, 1v range, lvds mode ltc2221: sfdr (hd4+) vs input frequency, ?db, 2v range, lvds mode ltc2221: sfdr (hd4+) vs input frequency, ?db, 1v range, lvds mode ltc2220/ltc2221 10 22201fa typical perfor a ce characteristics uw sample rate (msps) 0 sfdr and snr (dbfs) 160 2221 g10 40 80 120 140 20 60 100 100 95 90 85 80 75 70 65 60 sfdr snr sample rate (msps) 0 sfdr and snr (dbfs) 160 2221 g11 40 80 120 140 20 60 100 100 95 90 85 80 75 70 65 60 sfdr snr sample rate (msps) 0 i vdd (ma) 80 220 210 200 190 180 170 160 150 2221 g12 40 160 120 20 100 60 180 140 2v range 1v range sample rate (msps) 0 i ovdd (ma) 40 80 100 180 2221 g13 20 60 120 140 160 60 50 40 30 20 10 0 lvds outputs, ov dd = 3.3v cmos outputs, ov dd = 1.8v input levels (dbfs) C60 sfdr (dbc and dbfs) C50 C40 C30 C20 2221 g14 C10 100 90 80 70 60 50 40 30 20 10 0 0 dbfs dbc ltc2221: sfdr and snr vs sample rate, 2v range, f in = 30mhz, ?db, lvds mode ltc2221: sfdr and snr vs sample rate, 1v range, f in = 30mhz, ?db, lvds mode ltc2221: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2221: i ovdd vs sample rate, 5mhz sine wave input, ?db ltc2221: sfdr vs input level, f in = 70mhz, 2v range ltc2220/ltc2221 11 22201fa typical perfor a ce characteristics uw 2221 g18 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g19 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g20 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g23 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g22 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g21 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g15 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g16 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) 2221 g17 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C 100 C 110 C 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 frequency (mhz) amplitude (db) ltc2221: 8192 point fft, f in = 30mhz, ?db, 2v range, lvds mode ltc2221: 8192 point fft, f in = 30mhz, ?db, 1v range, lvds mode ltc2221: 8192 point fft, f in = 70mhz, ?db, 2v range, lvds mode ltc2221: 8192 point fft, f in = 70mhz, ?db, 1v range, lvds mode ltc2221: 8192 point fft, f in = 140mhz, ?db, 2v range, lvds mode ltc2221: 8192 point fft, f in = 140mhz, ?db, 1v range, lvds mode ltc2221: 8192 point fft, f in = 250mhz, ?db, 2v range, lvds mode ltc2221: 8192 point fft, f in = 250mhz, ?db, 1v range, lvds mode ltc2221: 8192 point fft, f in = 500mhz, ?db, 1v range, lvds mode ltc2220/ltc2221 12 22201fa (cmos mode) a in + (pins 1, 2): positive differential analog input. a in (pins 3, 4): negative differential analog input. refha (pins 5, 6): adc high reference. bypass to pins 7, 8 with 0.1 f ceramic chip capacitor, to pins 11, 12 with a 2.2 f ceramic capacitor and to ground with 1 f ceramic capacitor. reflb (pins 7, 8): adc low reference. bypass to pins 5, 6 with 0.1 f ceramic chip capacitor. do not connect to pins 11, 12. refhb (pins 9, 10): adc high reference. bypass to pins 11, 12 with 0.1 f ceramic chip capacitor. do not connect to pins 5, 6. refla (pins 11, 12): adc low reference. bypass to pins 9, 10 with 0.1 f ceramic chip capacitor, to pins 5, 6 with a 2.2 f ceramic capacitor and to ground with 1 f ceramic capacitor. v dd (pins 13, 14, 15, 62, 63): 3.3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. gnd (pins 16, 61, 64): adc power ground. enc + (pin 17): encode input. conversion starts on the positive edge. enc (pin 18): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1 f ceramic for single-ended encode signal. shdn (pin 19): shutdown mode selection pin. connect- ing shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 20): output enable pin. refer to shdn pin function. uu u pi fu ctio s db0 - db11 (pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): digital outputs, b bus. db11 is the msb. at high impedance in full rate cmos mode. ognd (pins 25, 33, 41, 50): output driver ground. ov dd (pins 26, 34, 42, 49): positive supply for the output drivers. bypass to ground with 0.1 f ceramic chip capacitor. ofb (pin 37): over/under flow output for b bus. high when an over or under flow has occurred. at high imped- ance in full rate cmos mode. clkoutb (pin 38): data valid output for b bus. in demux mode with interleaved update, latch b bus data on the falling edge of clkoutb. in demux mode with simulta- neous update, latch b bus data on the rising edge of clkoutb. this pin does not become high impedance in full rate cmos mode. clkouta (pin 39): data valid output for a bus. latch a bus data on the falling edge of clkouta. da0 - da11 (pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): digital outputs, a bus. da11 is the msb. ofa (pin 56): over/under flow output for a bus. high when an over or under flow has occurred. lvds (pin 57): output mode selection pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demux cmos mode with simulta- neous update. connecting lvds to 2/3v dd selects demux cmos mode with interleaved update. connecting lvds to v dd selects lvds mode. mode (pin 58): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and turns the clock duty cycle stabilizer off. connecting mode to 1/3v dd selects offset binary output format and turns the clock duty cycle stabi- lizer on. connecting mode to 2/3v dd selects 2s comple- ment output format and turns the clock duty cycle stabi- lizer on. connecting mode to v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. ltc2220/ltc2221 13 22201fa uu u pi fu ctio s sense (pin 59): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. connecting sense to v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 60): 1.6v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. (lvds mode) ain + (pins 1, 2): positive differential analog input. ain (pins 3, 4): negative differential analog input. refha (pins 5, 6): adc high reference. bypass to pins 7, 8 with 0.1 f ceramic chip capacitor, to pins 11, 12 with a 2.2 f ceramic capacitor and to ground with 1 f ceramic capacitor. reflb (pins 7, 8): adc low reference. bypass to pins 5, 6 with 0.1 f ceramic chip capacitor. do not connect to pins 11, 12. refhb (pins 9, 10): adc high reference. bypass to pins 11, 12 with 0.1 f ceramic chip capacitor. do not connect to pins 5, 6. refla (pins 11, 12): adc low reference. bypass to pins 9, 10 with 0.1 f ceramic chip capacitor, to pins 5, 6 with a 2.2 f ceramic capacitor and to ground with 1 f ceramic capacitor. v dd (pins 13, 14, 15, 62, 63): 3.3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. gnd (pins 16, 61, 64): adc power ground. enc + (pin 17): encode input. conversion starts on the positive edge. enc (pin 18): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1 f ceramic for single-ended encode signal. shdn (pin 19): shutdown mode selection pin. connect- ing shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 20): output enable pin. refer to shdn pin function. d0 /d0 + to d11 /d11 + (pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): lvds digital outputs. all lvds outputs require differential 100 ? termination resistors at the lvds re- ceiver. d11 C /d11 + is the msb. ognd (pins 25, 33, 41, 50): output driver ground. ov dd (pins 26, 34, 42, 49): positive supply for the output drivers. bypass to ground with 0.1 f ceramic chip capacitor. clkout /clkout + (pins 35 to 36): lvds data valid output. latch data on rising edge of clkout C , falling edge of clkout + . of /of + (pins 55 to 56): lvds over/under flow output. high when an over or under flow has occurred. lvds (pin 57): output mode selection pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demux cmos mode with simulta- neous update. connecting lvds to 2/3v dd selects demux cmos mode with interleaved update. connecting lvds to v dd selects lvds mode. ltc2220/ltc2221 14 22201fa uu u pi fu ctio s mode (pin 58): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and turns the clock duty cycle stabilizer off. connecting mode to 1/3v dd selects offset binary output format and turns the clock duty cycle stabi- lizer on. connecting mode to 2/3v dd selects 2s comple- ment output format and turns the clock duty cycle stabi- lizer on. connecting mode to v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin 59): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. connecting sense to v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 60): 1.6v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. ltc2220/ltc2221 15 22201fa fu n ctio n al block diagra uu w diff ref amp ref buf 2.2 f 1 f 0.1 f 0.1 f 1 f internal clock signals refh refl differential input low jitter clock driver range select 1.6v reference first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + refha reflb refla refhb enc C shift register and correction oe m0de ognd of ov dd d11 d0 clkout 22201 f01 input s/h sense v cm a in C a in + 2.2 f third pipelined adc stage output drivers control logic lvds shdn ? ? ? + C + C + C + C v dd gnd figure 1. functional block diagram ltc2220/ltc2221 16 22201fa t h t d t c t l n C 5 n C 4 n C 3 n C 2 n C 1 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc C enc + clockout C clockout + d0-d11, of 22201 td01 lvds output mode timing all outputs are differential and have lvds levels ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n analog input t h t d t c t l n C 5 n C 4 n C 3 n C 2 n C 1 enc C enc + clockoutb clockouta da0-da11, ofa db0-db11, ofb 22201 td02 high impedance full-rate cmos output mode timing all outputs are single-ended and have cmos levels ltc2220/ltc2221 17 22201fa t h t d t c t c t d t l n C 5 n C 3 n C 1 n C 6 n C 4 n C 2 enc C enc + clockoutb clockouta da0-da11, ofa db0-db11, ofb 22201 td03 t ap n + 1 n + 2 n + 4 n + 3 n analog input t h t d t c t d t l n C 6 n C 4 n C 2 n C 5 n C 3 n C 1 enc C enc + clockoutb clockouta da0-da11, ofa db0-db11, ofb 22201 td04 t ap n + 1 n + 2 n + 4 n + 3 n analog input demultiplexed cmos outputs with interleaved update all outputs are single-ended and have cmos levels demultiplexed cmos outputs with simultaneous update all outputs are single-ended and have cmos levels ti i g diagra s w u w ltc2220/ltc2221 18 22201fa applicatio s i for atio wu u u dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ( (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1) where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) converter operation as shown in figure 1, the ltc2220/ltc2221 is a cmos pipelined multistep converter. the converter has five pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applica- tions, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the encode input is differential for improved common mode noise immunity. the ltc2220/ltc2221 has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. ltc2220/ltc2221 19 22201fa each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is re- peated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2220/ ltc2221 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown at- tached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. c sample 1.6pf v dd v dd ltc2220/ltc2221 a in + 22201 f02 c sample 1.6pf v dd a in C enc C enc + 1.6v 6k 1.6v 6k c parasitic 1pf c parasitic 1pf 15 ? 15 ? figure 2. equivalent input circuit single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to 1.6v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for applicatio s i for atio wu uu ltc2220/ltc2221 20 22201fa the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.6v. the v cm output pin (pin 60) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2220/ltc2221 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of enc, the sample-and-hold circuit will connect the 1.6pf sam- pling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2220/ltc2221 being driven by an rf transformer with a center tapped secondary. the sec- ondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio trans- former. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transform- ers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequen- cies higher than 100mhz, the capacitor may need to be decreased to prevent excessive signal loss. 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in + a in C a in C 12pf 2.2 f v cm ltc2220/ ltc2221 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 22201 f03 figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? a in + a in + a in C a in C 12pf 2.2 f 3pf 3pf v cm ltc2220/ ltc2221 22201 f04 C C + + cm analog input high speed differential amplifier amplifier = ltc6600-20, lt1993, etc. figure 4. differential drive with an amplifier applicatio s i for atio wu uu figure 5. single-ended drive 25 ? 0.1 f analog input v cm a in + a in + a in C a in C 1k 12pf 22201 f05 2.2 f 1k 25 ? 0.1 f ltc2220/ ltc2221 ltc2220/ltc2221 21 22201fa the a in + and a in C inputs each have two pins to reduce package inductance. the two a in + and the two a in C pins should be shorted together. for input frequencies above 100mhz the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.6v. in figure 8 the series inductors are impedance matching elements that maximize the adc bandwidth. figure 7. recommended front end circuit for input frequencies between 250mhz and 500mhz reference operation figure 9 shows the ltc2220/ltc2221 reference circuitry consisting of a 1.6v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage reference can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differ- ential). tying the sense pin to v dd selects the 2v range; typing the sense pin to v cm selects the 1v range. the 1.6v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.6v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has four pins: two each of refha and refhb for the high reference and two each of refla and reflb for the low reference. the multiple output pins are needed to reduce package inductance. bypass capaci- tors must be connected as shown in figure 9. 25 ? 25 ? 0.1 f a in + a in + a in C a in C 2pf 2.2 f v cm ltc2220/ ltc2221 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 22201 f08 4.7nh 4.7nh applicatio s i for atio wu uu figure 6. recommended front end circuit for input frequencies between 100mhz and 250mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in + a in C a in C 8pf 2.2 f v cm ltc2220/ ltc2221 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 22201 f06 figure 8. recommended front end circuit for input frequencies above 500mhz 25 ? 25 ? 0.1 f a in + a in + a in C a in C 2.2 f v cm ltc2220/ ltc2221 analog input 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 22201 f07 v cm refha reflb sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.6v refla refhb 2.2 f 2.2 f internal adc high reference buffer 0.1 f 22201 f09 ltc2220/ltc2221 4 ? diff amp 1 f 1 f 0.1 f internal adc low reference 1.6v bandgap reference 1v 0.5v range detect and control figure 9. equivalent reference circuit ltc2220/ltc2221 22 22201fa other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.1v to 2.5v. each input may be driven from ground to v dd for single-ended drive. applicatio s i for atio wu uu v dd v dd ltc2220/ltc2221 22201 f11 v dd enc C enc + 1.6v bias 1.6v bias 1:4 0.1 f clock input 50 ? 6k 6k to internal adc circuits figure 11. transformer driven enc + /enc v cm sense 1.6v 0.8v 2.2 f 12k 1 f 12k 22201 f10 ltc2220/ ltc2221 figure 10. 1.6v range adc input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5db. see the typical performance character- istics section. driving the encode inputs the noise performance of the ltc2220/ltc2221 can depend on the encode signal quality as much as on the analog input. the enc + /enc C inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. differential drive should be used. maximum and minimum encode rates the maximum encode rate for the ltc2220/ltc2221 is 170msps (ltc2220) and 135msps (ltc2221). for the adc to operate properly, the encode signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 2.8ns (ltc2220) or 3.5ns (ltc2221) for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the enc + pin to sample the analog input. the falling edge of enc + is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock ltc2220/ltc2221 23 22201fa duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2220/ltc2221 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operat- ing frequency for the ltc2220/ltc2221 is 1msps. digital output modes the ltc2220/ltc2221 can operate in several digital out- put modes: lvds, cmos running at full speed, and cmos demultiplexed onto two buses, each of which runs at half speed. in the demultiplexed cmos modes the two buses (referred to as bus a and bus b) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). for details on the clock timing, refer to the timing diagrams. the lvds pin selects which digital output mode the part uses. this pin has a four-level logic input which should be connected to gnd, 1/3v dd , 2/3v dd or v dd . an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the lvds pin. applicatio s i for atio wu uu ltc2220/ltc2221 22201 f13a ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe figure 13a. digital output buffer in cmos mode digital outputs table 1. output codes vs input voltage a in + ?a in d11 ?d0 d11 ?d0 (2v range) of (offset binary) (2? complement) >+1.000000v 1 1111 1111 1111 0111 1111 1111 +0.999512v 0 1111 1111 1111 0111 1111 1111 +0.999024v 0 1111 1111 1110 0111 1111 1110 +0.000488v 0 1000 0000 0001 0000 0000 0001 0.000000v 0 1000 0000 0000 0000 0000 0000 C0.000488v 0 0111 1111 1111 1111 1111 1111 C0.000976v 0 0111 1111 1110 1111 1111 1110 C0.999512v 0 0000 0000 0001 1000 0000 0001 C1.000000v 0 0000 0000 0000 1000 0000 0000 ltc2220/ltc2221 25 22201fa applicatio s i for atio wu uu output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 1.8v supply then ov dd should be tied to that same 1.8v supply. in the cmos output mode, ov dd can be powered with any voltage up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . in the lvds output mode, ov dd should be connected to a 3.3v supply and ognd should be connected to gnd. output enable the outputs may be disabled with the output enable pin, oe. in cmos or lvds output modes oe high disables all data outputs including of and clkout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. the hi-z state is not a truly open circuit; the output pins that make an lvds output pair have a 20k resistance between them. therefore in the cmos output mode, adjacent data bits will have 20k resistance in between them, even in the hi-z state. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 35mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap mode all digital outputs are disabled and enter the hi-z state. grounding and bypassing the ltc2220/ltc2221 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital signal along- side an analog signal or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refha, refhb, refla and reflb pins as shown in the block diagram on the front page of this data sheet. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci- tors between refha and reflb and between refhb and refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the 2.2 f capacitor between refha and refla can be somewhat further away. the traces connect- ing the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2220/ltc2221 differential inputs should run par- allel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2220/ltc2221 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area. ltc2220/ltc2221 26 22201fa applicatio s i for atio wu uu clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the source to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi- layer pcbs. the differential pairs must be close together, and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. ltc2220/ltc2221 27 22201fa applicatio s i for atio wu uu evaluation circuit schematic of the ltc2220 a in + a in + a in C a in C refha refha reflb reflb refhb refhb refla refla v dd v dd v dd v dd v dd enc + enc C shdn oel ognd ognd ognd ognd v cm sense gnd gnd gnd mode lvds c16 0.1 f c11 0.1 f c39 0.1 f c34 4.7 f c33 0.1 f c32 0.1 f c30 0.1 f c31 0.1 f c17 1 f c7 12pf c18 1 f c19 2.2 f 1 2 3 4 5 6 7 8 9 10 11 12 62 63 13 14 15 17 18 19 20 25 33 41 50 60 59 16 61 64 58 57 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21 49 42 34 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 clk clk c29 2.2 f v cm v cm v dd v cm v dd v dd v dd v dd v dd v dd v dd mode r28 1k r29 1k r2 4.99k 1% r3 4.99k 1% r4 4.99k 1% r30 1k 2/3v dd 1/3v dd gnd jp7 jp20 c35 0.1 f c21 0.1 f c24 0.1 f c36 4.7 f c12 0.1 f c10 0.1 f c8 0.1 f c9 0.1 f c6 0.1 f c5 0.1 f c4 0.1 f c5 4.7 f c2 0.1 f c1 0.1 f sense ext ref gnd gnd en/12 rin1 C rin1 + rin2 + rin2 C rin3 C rin3 + rin4 + rin4 C v cc en rin5 C rin5 + rin6 + rin6 C rin7 C rin7 + rin8 + rin8 C en/34 gnd v bb v cc v cc en/78 dout1 C dout1 + dout2 + dout2 C dout3 C dout3 + dout4 + dout4 C gnd gnd dout5 C dout5 + dout6 + dout6 C dout7 C dout7 + dout8+ dout8 C en/56 v cc v cc r13 100 ? r1 100 ? r26 100 ? r25 100 ? r24 100 ? r23 100 ? r21 100 ? r14 100 ? r15 100 ? r16 100 ? r17 100 ? r20 100 ? r18 100 ? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v dd v dd v cc v ss v cc_in v cc v cc v cc opt v cc 3.3v l1 murata blm18bb470sn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd en/12 rin1 C rin1 + rin2 + rin2 C rin3 C rin3 + rin4 + rin4 C v cc en rin5 C rin5 + rin6 + rin6 C rin7 C rin7 + rin8 + rin8 C en/34 gnd v bb v cc v cc en/78 dout1 C dout1 + dout2 + dout2 C dout3 C dout3 + dout4+ dout4 C gnd gnd dout5 C dout5 + dout6 + dout6 C dout7 C dout7 + dout8 + dout8 C en/56 v cc v cc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc v cc a0 a1 a2 a3 v cc wp scl sda jp4 1 2 3 4 8 7 6 5 scl sda r19 100 ? 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 pwr gnd gnd v dd v dd 3.3v c3 4.7 f c22 0.1 f c27 0.1 f c23 0.1 f r27 50 ? r9 24.9 ? r10 24.9 ? r12 24.9 ? r11 24.9 ? v cm analog input ain + ain + ain C ain C c20 0.1 f c25 33pf c26 0.1 f r8 100 ? r7 100 ? encode input clk clk t2 etc1-1t t1* etc1-1t edge-con-100 r6 4.7k v ss scl sda v cc_in v cc enable of + /ofa of C /da11 d11 + /da10 d11 C /da9 d10 + /da8 d10 C /da7 d9 + /da6 d9 C /da5 d8 + /da4 d8 C /da3 d7 + /da2 d7 C /da1 d6 + /da0 d6 C /clkouta d5 + /clkoutb db5 C /ofb clkout + /db11 clkout C /db10 d4 + /db9 d4 C /db8 d3 + /db7 d3 C /db6 d2 + /db5 d2 C /db4 d1 + /db3 d1 C /db2 d0 + /db1 d0 C /db0 ov dd ov dd ov dd ov dd enable ltc2220 jp3 jp1 shdn gnd gnd 0e j9 j6 u4 24lco25 * for ain > 100mhz, replace t1 with a etc1-1-13 u3 u1 finii08 u2 finii08 ltc2220/ltc2221 28 22201fa applicatio s i for atio wu uu silkscreen top ltc2220/ltc2221 29 22201fa applicatio s i for atio wu uu layer 1 component side layer 2 gnd plane ltc2220/ltc2221 30 22201fa applicatio s i for atio wu uu layer 4 bottom side layer 3 power plane ltc2220/ltc2221 31 22201fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) package descriptio u 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom viewexposed pad 7.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (up64) qfn 1003 recommended solder pad pitch and dimensions 0.70 0.05 7.15 0.05 (4 sides) 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer ltc2220/ltc2221 32 22201fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0106 rev a ? printed in usa related parts part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt ? 1994 low noise, low distortion fully differential input/ low distortion: C94dbc at 1mhz output amplifier/driver ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220 12-bit, 170msps, 3.3v adc, lvds outputs 890mw, 67.7db snr, 84db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2221 12-bit, 135msps, 3.3v adc, lvds outputs 660mw, 67.8db snr, 84db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2230 10-bit, 170msps, 3.3v adc, lvds outputs 890mw, 61.2db snr, 78db sfdr, 64-pin qfn ltc2231 10-bit, 135msps, 3.3v adc, lvds outputs 660mw, 61.2db snr, 78db sfdr, 64-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver with digitally 450mhz to 1db bw, 47db oip3, digital gain control controlled gain 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz. nf = 12.5db, 50 ? single ended rf and lo ports |
Price & Availability of LTC2221CUPTR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |